?002 fairchild semiconductor corporation IRFP9140 rev. b IRFP9140 19a, 100v, 0.200 ohm, p-channel power mosfet this is an advanced power mosfet designed, tested, and guaranteed to withstand a speci?d level of energy in the breakdown avalanche mode of operation. it is a p-channel enhancement mode silicon gate power ?ld effect transistor designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. formerly developmental type ta17521. features 19a, 100v ? ds(on) = 0.200 ? single pulse avalanche energy rated soa is power dissipation limited nanosecond switching speeds linear transfer characteristics high input impedance symbol packaging jedec style t0-247 ordering information part number package brand IRFP9140 to-247 IRFP9140 note: when ordering, use the entire part number. g d s drain (flange) source drain gate data sheet january 2002
?002 fairchild semiconductor corporation IRFP9140 rev. b absolute maximum ratings t c = 25 o c, unless otherwise speci?d IRFP9140 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ds -100 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr -100 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d t c =100 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm -19 -12 a a pulsed drain (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm -76 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p d 150 w linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 w/ o c single pulse avalanche energy rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as 960 mj operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss v gs = 0v, i d = -250 a, (figure 10) -100 - - v gate threshold voltage v gs(th) v ds = v gs , i d = -250 a -2.0 - -4.0 v zero gate voltage drain current i dss v ds = rated bv dss , v gs = 0v - - 25 a v ds = 0.8 x rated bv dss , v gs = 0v, t j = 125 o c - - 250 a on-state drain current (note 2) i d(on) v ds > i d(on) x r ds(on) max , v gs = -10v -19 - - a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) v gs = -10v, i d = -10a, (figures 8, 9) - 0.14 0.20 ? forward transconductance (note 2) g fs v ds -50v, i d = -10a, (figure 12) 5.3 7.9 - s turn-on delay time t d(on) v dd = -50v, i d -19a, r g = 9.1 ?, r l = 2.5 ?, v gs = -10v, (figures 17, 18) mosfet switching times are essentially indepen- dent of operating temperature - 16 20 ns rise time t r - 65 100 ns turn-off delay time t d(off) -4770ns fall time t f -2870ns total gate charge (gate to source + gate to drain) q g(tot) v gs = -10v, i d = -19a, v ds = 0.8 x rated bv dss, i g(ref) = -1.5ma (figures 14, 19, 20) gate charge is essentially independent of operating temperature -3755nc gate to source charge q gs - 8.7 - nc gate to drain ?iller?charge q gd -22- nc input capacitance c iss v gs = 0v, v ds = -25v, f = 1.0mhz, (figure 11) - 1200 - pf output capacitance c oss - 570 - pf reverse transfer capacitance c rss - 160 - pf internal drain inductance l d measured between contact screw on header that is closer to source and gate pins and center of die modified mosfet symbol showing the in- ternal device induc- tances - 5.0 - nh internal source inductance l s measured from the source pin, 6mm (0.25in) from header and source bond- ing pad -13- nh junction to case r jc - - 0.83 o c/w junction to ambient r ja free air operation - - 30 0 c/w l s l d g d s IRFP9140
?002 fairchild semiconductor corporation IRFP9140 rev. b source to drain diode speci?ations parameter symbol test conditions min typ max units continuous source to drain current i sd modified mosfet symbol showing the integral re- verse p-n junction diode - - -19 a pulse source to drain current (note 3) i sdm - - -76 a source to drain diode voltage (note 2) v sd t j = 25 o c, i sd = -19a, v gs = 0v, (figure 13) - - -1.5 v reverse recovery time t rr t j = 25 o c, i sd = -18a, di sd /dt = 100a/ s - 210 - ns reverse recovery charge q rr t j = 25 o c, i sd = -18a, di sd /dt = 100a/ s - 2.0 - c notes: 2. pulse test: pulse width 80 s, duty cycle 2%. 3. repetitive rating: pulse width limited by maximum junction temperature. see transient thermal impedance curve (figure 3). 4. v dd = 50v, start t j = 25 o c, l = 4.2mh, r g = 25 ?, peak i as = 19a. see figures 15, 16. typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized transient thermal impedance g d s t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 20 16 12 8 4 0 i d , drain current (a) 25 50 75 100 125 150 t c , case temperature ( o c) single pulse 1 0.1 10 -2 10 -3 z jc, normalized 10 -5 10 -4 10 -3 10 -2 0.1 1 10 t 1 , rectangular pulse duration (s) 0.05 0.2 0.1 0.05 0.02 0.01 thermal impedance p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c IRFP9140
?002 fairchild semiconductor corporation IRFP9140 rev. b figure 4. forward bias safe operating area figure 5. output characteristics figure 6. saturation characteristics figure 7. transfer characteristics figure 8. drain to source on resistance vs gate voltage and drain current figure 9. normalized drain to source on resistance vs junction temperature typical performance curves unless otherwise speci?d (continued) i ds , drain to source current (a) v ds , drain voltage (v) 100 10 1 0.1 1 10 100 operation in this area is limited by r ds(on) t c = 25 o c t j = max rated single pulse 10 s 100 s 1ms 10ms 100ms dc 24 pulse duration = 80 s v ds , drain to source voltage (v) v gs = -10v v gs = -8v v gs = -6v v gs = -5v v gs = -4v 30 18 12 6 0 i ds , drain to source current (a) 0 -10 -20 -30 -40 -50 v gs = -7v duty cycle = 0.5% max 30 24 18 12 6 0 i ds , drain to source current (a) 012 345 v ds , drain to source voltage (v) v gs = -10v v gs = -8v v gs = -6v v gs = -7v v gs = -5v v gs = -4v pulse duration = 80 s duty cycle = 0.5% max v gs , drain to source voltage (v) t j = 150 o t j = 25 o 10 2 10 1 0.1 0246810 i ds , drain to source current (a) pulse duration = 80 s duty cycle = 0.5% max v ds -50v 1.5 1.2 0.9 0.6 0.3 0 r ds(on), drain to source 0 16324864 80 i d , drain current (a) v gs = -10v v gs = -20v on resistance ( ? ) pulse duration = 80 s duty cycle = 0.5% max 3.0 2.4 1.8 1.2 0.6 0 normalized drain to source on resistance v gs = -10v -60 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( o c) pulse duration = 80 s duty cycle = 0.5% max IRFP9140
?002 fairchild semiconductor corporation IRFP9140 rev. b figure 10. normalized drain to source breakdown voltage vs junction temperature figure 11. capacitance vs drain to source voltage figure 12. transconductance vs drain current figure 13. source to drain diode voltage figure 14. gate to source voltage vs gate charge typical performance curves unless otherwise speci?d (continued) 0.75 0.85 0.95 1.05 1.15 1.25 normalized drain to source -60 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( o c) i d = 250 a breakdown 2000 2500 1500 1000 500 0 c, capacitance (pf) 110 10 2 negative v ds , drain to source voltage (v) c rss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd c oss c iss 0 3 6 9 12 15 g fs , transconductance (s) 0 8 16 24 32 40 negative i d , drain current (a) t j = 150 o c t j = 25 o c pulse duration = 80 s duty cycle = 0.5% max v ds -50v t j = 25 o c t j = 150 o c -100 -10 -1.0 -0.1 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 negative v sd , source to drain voltage (v) i sd , source to drain current (a) pulse duration = 80 s duty cycle = 0.5% max 20 16 12 8 4 0 v gs , gate to source 01224364860 q g(tot) , total gate charge (nc) v ds = -80v v ds = -50v v ds = -20v i d = -19a voltage (v) IRFP9140
?002 fairchild semiconductor corporation IRFP9140 rev. b test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. switching time test circuit figure 18. resistive switching waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms t p 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v gs v dd v ds bv dss t p i as t av 0 v gs r l r g dut + - v dd t d(on) t r 90% 10% v ds 90% t f t d(off) t off 90% 50% 50% 10% pulse width v gs t on 10% 0 0 0.3 f 12v battery 50k ? +v ds s dut d g i g(ref) 0 (isolated -v ds 0.2 f current regulator i d current sampling i g current sampling supply) resistor resistor dut q g(tot) q gd q gs v ds 0 v gs v dd 0 i g(ref) IRFP9140
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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